Bipolar and GaAs technologies have been the RF workhorses for the designers of digital wireless devices such as cellular and cordless telephones. But that is changing as increased integration favors BiCMOS, SiGe and CMOS processes.

BiCMOS had to be used for the front end in such wireless applications as GSM or DECT because standard CMOS did not provide adequate noise performance, sensitivity andoutput power. However, the Bluetooth standard now makes RF implementation in CMOS feasible. In fact, recent comparisons of the various available technologies have shown that CMOS is the most effective for Bluetooth chip sets. But adding up the strengths of those technologies and the trade-offs they demand,and factoring in today's focus on cost minimization, makes CMOS the logical choice for Bluetooth. Here's why.

When setting out to design the circuitry of a wireless communications device, such as a mobile or cordless phone or a wireless LAN card, the engineer is confronted with a number of concerns, notably:

• The wireless challenge: Designing a wireless system is more difficult than designing a digital circuit. Several circuits with quite different functions have to be accommodated on a single silicon substrate.
• Technology options: The choice of available technologies is extensive and is primarily defined in collaboration with fabs located in the Far East. Analog, digital, RF,WAP, battery management, memory and interfaces mean that the designer of a modern wireless device needs wide-ranging expertise.
• Reuse considerations: The ever-increasing complexity of silicon chip circuitry is driving manufacturers to develop strategies for reuse.
• Market demands: Wireless devices are rapidly overtaking the PC as the prime application area for silicon chip technologies.
• Cost: As with all modern consumer electronics, cost is a major factor.
• International standards: Despite the application of international standards, there are still technical differences between countries that have to be accommodated during the design phase.

Undeniably, the central feature of the design constraints is increasing system complexity -- individual designers, design departments or design companies all face them.What this inevitably means is that all these technologies and skills have to be acquired.

To maintain a leadership position in the wireless market,a manufacturer has to have access to a wide variety of silicon technologies in smaller packages,good design tools and a mastery of complex designs. In this respect, there is no substitute for long experience in the manufacturing of mobile and cordless phones combined, with expertise in the design of reusable chips.

The basic block schematic for a mobile telephone is reasonably universal. It will be evident that each of the circuit blocks shown has very different functions -- in it -- self not such a dramatic revelation as even basic analog radio circuitry is composed of several different functional elements. However, in mobile telephone circuitry we have to consider that each circuit block represents a different IC. If we now take that one step further, we can see that each of those silicon chips has very different functions and its internal components require quite different characteristics.

This means that there is no way all these circuits can employ the same type of silicon technology. For instance,experience has taught us that CMOS is the most suitable technology to employ for digital, especially for large volume production. The digital CMOS road map shows that about every six months a new generation is developed, going up the micron ladder from 0.5 to 0.35 to 0.25 to 0.18 to 0.13 and so on. As soon as 0.10 micron is available,it will be adopted for high-volume digital ICs. This progress is led by design partnerships with the Far Eastern megafabs; our design capability has to follow the materials they can make available to us.

Design compromises
Any engineer developing silicon technology knows that in CMOS there is always a trade-off between gate delays and leakage current. However, although leakage current is not that critical in PC circuit design it is of enormous importance to the wireless circuit designer. In practice, the area of the silicon is determined more by memory than gate density. These days, chip fabricators are being encouraged to adapt their technologies more toward digital wireless circuit requirements.

We can see the kind of progress being made if we consider that in 1999 a 0.25-micron CMOS IC needed 40mm2 for 1 million gates or 15mm2 for 1 Mbyte of static RAM.By 2003, we expect this to be reduced to 3mm2 for 1 million gates or 2mm2 for 1 Mbyte of RAM. This evidently means that we are able either to place considerably more components on the same slice of silicon or reduce the size of the chips and pack more chips into the same device.

For low-frequency analog circuitry,things are a little different. There we have to integrate such things as A/D converters, filters, amplifiers and control logic. We may also be able to combine the LF block with the baseband processor or the RF front end. It is important to note that the CMOS we use for analog circuits is not the same CMOS used for digital circuitry.That 's because digital circuits are composed of transistors but analog circuits also require resistors, capacitors and inductors.

A single substrate
Combining digital and analog circuitry on the same substrate presents a number of difficulties. For instance, we have to consider yield rates. Integrating analog and digital on one die implies that a large fully functional digital circuit might have to be scrapped because of parametric deviations in the small analog portion present on the same die. Testing is also much more difficult for analog circuits,especially when they are integrated with digital circuitry. Supply voltage is another area in which analog and digital circuits differ. Digital circuit voltages are steadily decreasing while those of analog circuits are still relatively high. All in all, mixing digital and analog technologies on the same chip is difficult but is desirable in certain circumstances.

The road map for analog technologies shows that analog is trailing digital by about one year. The reason is that within any design program digital development is treated as a priority and analog is dealt with later.

In the RF front end,several technologies are employed -- we have to combine low-noise amplifiers, mixers, filters, RF amplifiers and power amplifiers. These devices can be made in CMOS but they more commonly use bipolar or BiCMOS. If CMOS is used, it is again not the same as digital CMOS because resistors, capacitors and inductors are required. Once again there has to be a trade-off between the cost of the chip and the cost of discrete components. It makes no sense to strive for a low chip cost only to find that the additional cost of external components makes the overall cost higher. In the mobile telephone market, the total cost of the handset is the driving factor, so component costs have to be finely balanced.

Other trade-offs are performance and time-to-market. After all,there is no value in spending five years developing a very inexpensive chip if in the meantime your competitors have grabbed the market with their medium-cost product. This argument is exemplified in the case of RF CMOS. It may come eventually but development times are still too long and cannot be justified economically.

Consequently, SiGe BiCMOS still seems to be one of the most viable technologies for RF circuits. However, BiCMOS technology is perhaps two years behind that of standard digital CMOS. Furthermore, progress is being made with silicon-germanium-carbon technology to produce RF BiCMOS circuits.

Battery-management circuitry requires high-precision reference voltages, a dc/dc converter, low-drop output regulators, series regulators and battery-monitoring circuits. In practice, the battery-management chip has also become a repository for a number of other circuits that have no specific home -- for instance, the SIM interface, the audio codec or auxiliary interfaces that have nothing to do with battery management. The voltage levels in the battery-management circuit are generally much higher than those in the other circuits (typically 20 Vdc). This is because the voltage supplied by external charging sources (car or power-network derived) has a large tolerance and can vary by as much as 6 to 20 V.

The battery-management chip can use CMOS, DMOS or bipolar-CMOS-DMOS. This is analog circuitry with resistors and capacitors, sometimes together with one-time-programmable memory to enable the phone manufacturer to embed a code to restrict the use of the device. There may also be some digital control circuitry. This mixed-mode I 2 T intelligent interface technology is derived from 0.7-micron CMOS. This exists in 100-, 60- and 30-V versions,with the battery manager made in the 30-V version. There is an I 3 T version in the pipeline that is based on 0.35-micron CMOS, and some development is taking place in SOI for these relatively high-voltage devices.

So it can be seen that mobile telephones require a variety of silicon technologies, but it is very difficult to put all of these different circuits on the same die. Each of the blocks in the schematic has its own trade-offs for component type and density, operating voltage, functionality, etc.

Design reuse is not a compromise
The second consideration is design reuse. This necessity is imposed on the industry because every two years component density is doubled while design productivity does not increase at the same pace, making the design area a rapidly tightening bottleneck.

So the intelligent reuse of building blocks is becoming more and more necessary. In fact, intellectual property companies are being established to market such designs, usually in the form of VHDL software packages that can be used for the manufacture of the necessary chip sets, evidently helping to shorten the design cycle and bypass the bottleneck.

Designing finished products based on IP building blocks also presents some difficulties. After transformation of the system-level specification into a high-level language, the process can follow three directions; digital synthesis is relatively straightforward, but there is no current procedure for analog synthesis and we have to go back to the drawing board or CAD for analog circuit design and layout.

The third direction is software development, to deal primarily with microprocessor control. Between analog design and digital synthesis we have the possibility of performing mixed-mode simulation and evidently have the need to simulate or co-simulate the software together with the digital firmware. So far, there are no tools available to handle all three processes.

Very complex digital blocks are now available from IP vendors. However,analog circuits tend to be designed for specific applications, and there is no universal standard that enables analog blocks to be transportable from one fab to another. In practice, a company can design and reuse its own analog building blocks; however, it is generally not practical for the IP vendors to offer such circuits at a useful level.

The future with Bluetooth
The aim is to create a very small, inexpensive device that will provide reliable communication over short distances: no more than 10 to 15 meters. What has been stated earlier might seem to make BiCMOS the obvious choice for the Bluetooth radio section. However, Bluetooth specifications are less demanding than those for GSM or DECT, so we can now consider CMOS as a realistic technology for the design of a Bluetooth wireless device. The block diagram is virtually the same as that of the GSM and DECTdevices but with everything built on the same relatively inexpensive CMOS die.

So technology continues its relentless advance, despite the constraints of cost.

Even though the reuse life cycle may be quite short, the more extensively a circuit can be reused will contribute greatly to the ability of the final product manufacturer to continue responding to competitive market demands for overall cost reduction.